1. Field of the Invention
The invention relates to a fuse detecting apparatus.
2. Description of Related Art
In a present integrated circuit, a so-called “fusing” technique is generally used to achieve effects of selecting functions or adjusting an output voltage level. In brief, one or a plurality of fuses is blown to form open circuits or is not blown to form short circuits to generate more than one combinations, so as to set functions to be selected or output voltage levels to be generated. Once determining of a fuse status goes wrong, an operation of the whole integrated circuit is incorrect, which may cause an irredeemable error.
Referring to FIG. 1, FIG. 1 is a diagram illustrating a conventional fuse detecting apparatus. The fuse detecting apparatus 100 includes transistors P1 and N1 serving as switches, transistors P2, P3, N2 and N3 used for constructing a latch, and an inverter INV1. The fuse detecting apparatus 100 is used for detecting a short circuit state or an open circuit state of a fuse FUSE. Operation details of the fuse detecting apparatus 100 are described with reference of FIG. 2, and FIG. 2 is a signal waveform diagram of the fuse detecting apparatus 100. First, a reference voltage VINT serving as a power voltage that is received by the fuse detecting apparatus 100 is enabled and gradually increases to a stable state. Meanwhile, a control signal bFPUP is enabled (maintained to a logic low level) to turn on the transistor P1. Now, the latch formed by the transistors P2, P3, N2 and N3 latches a received signal (logic high level) equivalent to the reference voltage VINT, and outputs a detecting signal bFLATS with the logic low level through the inverter INV1. Then, the control signal bFPUP is transited to the logic high level (which is disabled) to turn off the transistor P1, and another control signal FPUN is enabled (transited to the logic high level) to turn on the transistor N1. In case that the fuse is not blown (the short circuit state), the latch formed by the transistors P2, P3, N2 and N3 latches a ground voltage VSS to transit the detecting signal bFLATS into a logic high level signal.
It should be noticed that although the fuse in the fuse detecting apparatus has the short circuit state, during a time period T1, the detecting signal bFLATS used for representing the status of the fuse FUSE presents an open circuit state (logic level) which represents that the fuse FUSE is blown down. Namely, the conventional fuse detecting apparatus 100 is liable to generate misjudgement.